Research Overview
Towards Reliability-Aware DTCO — building a multi-scale simulation chain from atomic defect structures through device degradation to circuit aging.
Starting from first-principles calculation of gate-dielectric defect properties, extending to large-scale systems via MLIP, predicting device-level ΔVth degradation through the All-state Model and the in-house simulator RASP, and reaching circuit-level aging & timing assessment through Compact Model development.
Addressing the core DTCO question — "which defects dominate degradation?" — by developing defect density extraction methods based on inverse theory, recovering atomic-level defect parameters from electrical measurements to close the simulation-experiment loop.
DFT / MLIP
All-state Model / RASP
Compact Model / HSPICE
Education
Research Achievements
Atomic-Level Defect Property Simulation
- High-throughput defect calculation: Systematic first-principles study of intrinsic defect properties in SiO2, HfO2 and other gate dielectrics; established defect database.
- Software development: Led development of ILED (Intelligent Learning Engine of Defects) for one-stop automated IC material defect property calculation; contributed to core modules of DASP (Defect & Dopant Ab-Initio Simulation Package).
ML-Accelerated Defect Property Calculation
- AI acceleration: Introduced MLIP to accelerate defect search, reducing computational cost to 7.36% of DFT while maintaining >96% accuracy.
Device-Level Reliability Simulation Methods & Software
- High-throughput computation: Systematic study of oxygen vacancies in amorphous SiO2, discovering 7 stable configurations with wide energy distributions.
- Model innovation: Proposed the "All-state Model" for Si/SiO2 MOSFETs, correcting critical errors in traditional models caused by missing defect paths in amorphous gate dielectrics. This model is being integrated into a leading domestic TCAD simulator.
- Software development: Led development of RASP, enabling cross-scale reliability simulation from atomic defect parameters to device-level threshold voltage shifts.
Defect Parameter Extraction from Electrical Measurements
- Formulated BTI ΔVth degradation as a non-negatively constrained Fredholm first-kind integral equation inverse problem. Solved the ill-conditioned linear system via SVD analysis, Tikhonov regularization, and PLS dimensionality reduction to extract NMP defect density distributions from single-set electrical measurements.
Circuit-Level Aging Compact Model Development
- Model innovation: Developing MOSFET and FinFET circuit-level aging models based on the "All-state Model".
- Atomic-resolution circuit aging simulation: Combining in-house defect parameter extraction methods with HSPICE to build a complete atomic-to-circuit aging simulation chain.
Software Development
RASP
Core Developer 2024 – PresentReliability Ab initio Simulation Package
All-state model based reliability simulation package. Enables cross-scale simulation from first-principles defect parameters to device-level ΔVth prediction.
Documentation & User ManualILED
Core Developer 2023 – PresentIntelligent Learning Engine of Defects
One-stop automated IC material defect property calculation software (copyrighted). Integrates MLIP for rapid defect screening.
DASP
Contributor 2022 – 2023Defect & Dopant Ab-Initio Simulation Package
Contributed to core modules. Now commercially deployed with 150+ users across academia and industry, including Huawei HiSilicon.
Selected Publications
- "Si/SiO2 MOSFET reliability physics: From four-state model to all-state model." Physical Review Applied 24, 044040, 2025.
- "RASP: Reliability ab initio simulation package of MOSFETs based on all-state model." Microelectronics Reliability, Under Review.
- "An overlooked origin of NBTI in Si based MOSFETs." IEEE Electron Device Letters, Submitted.
- "Machine learning interatomic potentials accelerate defect exploration in amorphous silica." Physical Review Materials, 2025.
- "DASP: Defect and Dopant Ab-Initio Simulation Package." Journal of Semiconductors 43, 042101, 2022.